1. Field of the Present Invention
The present invention relates generally to semiconductor devices designed from industry standard existing standard-cell ASIC libraries, and, in particular, to an architecture where all semiconductor layer masks are reusable except for two non-adjacent via layers which are used to configure the device.
2. Background
For many years, gate array semiconductor devices have been used to provide quick-turnaround (“quick-turn”), low non-recurring-expense (“NRE”) semiconductor devices for a variety of purposes. Traditionally, semiconductor wafers are processed up to but not including the first (bottom) metal layer, and saved in inventory. When a customer orders a semiconductor device to be fabricated for a specific application (an application-specific integrated circuit or “ASIC”), the customer only pays for the semiconductor layer masks (“masks”) to configure the metal layers, including both the metal routing layers and via layers, but not the transistor layers below. Thus, NRE is reduced. The wafers can be completed quickly, since only the metal routing layers and via layers remain to be fabricated, reducing turn-around time.
Recently more and more layers of metal have been incorporated into gate array semiconductor devices, more commonly known simply as “gate arrays.” Rather than using two or three layers of metal, six to eight layers of metal, including both metal routing layers and the via layers used to connect one metal routing layer to the metal routing layer directly above or below, are now common. As a result, gate arrays are often no longer very low-NRE, or quick-turn. In order to regain the advantages of earlier gate arrays, several vendors have developed logic arrays, consisting of multiple, substantially identical logic cells, which can be configured for an application with fewer or cheaper masks. These types of gate arrays are commonly known as structured ASICs. Notably, although fewer masks are required to configure these ASICs, it is not the total number of metal layers and hence masks used to create the finished or customized device that is reduced. Rather, the number of masks required to impart the custom configuration to the device is reduced to only a subset of the total number of metal layers in a finished device. For example, so-called “one-mask” devices, in which only a single metal layer and hence a single mask imparts customization, can in theory reduce both NRE and turn-time.
Structured ASICs are a well-known solution for reducing mask costs when fabricating a semi-custom integrated circuit chip. These ASICs combine large numbers of programmable blocks of logic devices into an array of logic cells to create a device that is specifically adapted for a particular application, but at a cost that is lower than that of developing a completely new logic cell from scratch. Most structured ASICs use industry standard libraries of standard-cells, supported by large Electronic Design Automation (EDA) companies. Standard-cells are small logic cells with predefined design characteristics such as their layout, timing, and other electrical characteristics. Each group of logic devices that has a unique physical layout is defined as one standard-cell. The library contains files that include the layout, timing and other electrical characteristics for each standard-cell in the library. The structured ASICs combine groups of standard-cells to form larger logic cells to create a device that is specifically adapted for a particular application.
After the logic cells of the structured ASIC are mapped or designed from the standard-cells, they are then arrayed, and then the metal layers to connect the logic cells are generated. The process of arraying the logic cells and generating the metal layers is commonly referred to as the place and route process. Most non-structured ASICs use place and route tools from major vendors, such as Cadence, Synopsys, or Magma, that are designed for use with these standard-cell libraries in a full custom design. However, when applied to structured ASICs, these tools have limitations that restrict how they route signals, i.e., they route signals only on full custom routing layers and via layers. For example, if a structured ASIC has six custom metal layers (i.e., three via layers and three metal routing layers), then only three metal routing layers can be used to route signals and the three via layers to connect them.
Furthermore, when the current place and route tools are used to route these signals, they impart certain rules and restrictions on how each layer is routed. For example, they may require two metal routing layers (“METAL2” and “METAL4”) to run horizontally, and may require a third metal routing layer (“METAL3”) to run vertically. The way the via layers are cut to connect the metal routing layers also has restrictions in the place and route tool. Also, the tool will not allow routing or via connections between fixed metal routing layers already incorporated into the logic array or the fixed logic cells, including METAL1 and possibly some METAL2. These rules and restrictions are built into the tools and optimized for full custom ASICs to achieve the highest density logic and routing. Unfortunately, the tools are not designed to achieve logic mask reuse and thus avoid NRE.
By carefully controlling the way the standard-cell libraries are designed, not necessarily using the industry standard libraries, and by carefully controlling the way the metal layers are created in the structured ASIC architecture, not necessarily using the major vendors' place and route tools designed for full custom ASICs, the number of custom masks that may be required may often be reduced to just one mask. Using a single via layer to customize a semiconductor device is one technology for creating “one-mask” devices. Significant advantages of single via configuration are low configuration cost and faster turn-around time. The single via configuration is completed by first fabricating the semiconductor transistor layers for the mask configurable gate array as described above. Then, the plurality of metal layers are fabricated on top which creates a specialized logic array that has the characteristics which enable the specialized place and route tool to route and connect signals on and between the fixed metal routing layers using a single via layer. Single via layer configuration is more fully disclosed in U.S. Pat. No. 6,580,289 to Cox (the “'289 patent”), the entirety of which is incorporated herein by reference.
However, single via configuration also comes at a steep price: over twice the area is required to complete routing as compared to using standard-cells from an industry standard library and using an industry standard place and route tool. One solution to this problem is to use embedded distributed SRAM which gives the ASICs more than double the area for routing. The embedded distributed SRAM solution is more fully disclosed in U.S. Pat. No. 6,693,454 to Cox, the entirety of which is incorporated herein by reference. The embedded distributed SRAM structured ASICs have proven to have the lowest production cost of any structured ASIC, both in terms of total die area, and mask costs.
Unfortunately, although the single via configuration with embedded distributed SRAM offers many advantages for semiconductor designers, there are still significant market barriers to the adoption of this process. For example, for a customer to use the single via configuration with the embedded distributed SRAM process, it requires them to use non-industry standard standard-cell and macro libraries. As stated previously, most customers only use the industry standard libraries supported by large EDA companies such as Cadence, Synopsys, and Magma. Unfortunately, customers are reluctant to adopt custom libraries and add the additional time and expense of maintaining an additional set of libraries for synthesis, timing analysis, and the like. Customers have also had concerns about the large area over which the logic is spread, especially when they were not using the distributed SRAM. When the high cost of developing a custom library for a new fabrication process is added to the long development time of the new library, the market barriers become prohibitive in many cases.
Accordingly, a need exists for a new solution to address these issues while still maintaining many of the benefits of the single via configuration process.